Increasing workload demands have created the need for high capacity, high performance memory subsystems in system platforms. Memory subsystems in multi-processor (or multi-core) servers, such as 4-socket and 8-socket server configurations, typically include large amounts of main memory capacity.
Current high capacity memory subsystem solutions result in high power consumption even when the system platform is completely idle. The result is that memory subsystem idle power is a significant component of the overall system platform idle power consumption. There is an increasing demand for significant reduction in system platform idle power consumption. What is needed is a solution to reduce the memory subsystem idle power consumption, and thereby reducing the overall system platform idle power consumption, without adversely affecting system memory links and without sacrificing memory performance.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the invention is provided below, followed by a more detailed description with reference to the drawings.